Some emerging re-configurable logic device architectures comprise grids of repeating re-configurable logic blocks. In some such architectures, each block comprises a program memory and connection means for inputting and outputting programming data into and out from the program memory. When these blocks are interconnected, the connection means link together to form chains of blocks. When several chains are placed side by side, an array of blocks can be created.
Each array is a hard-macro. That is to say that each array is preconfigured with physical pathways and wiring patterns between its components. Accordingly, once the array is hardwired, it is difficult, if not impossible, to reconfigure it. There are several different types of arrays, each of which provide specific advantages.
For example, one type of array is a fully parallel array. The fully parallel array comprises several chains of blocks, the beginnings and ends of which are each connected to a programming interface. The fully parallel array provides the advantage of being able to be configured quickly. However, the programming interfaces necessary to configure this type of array will need to be more complex and will therefore have more overhead.
Another type of array is the fully serial array. The fully serial array comprises a single chain of blocks made of smaller interconnected chains of blocks. The beginning and end of this chain of blocks will be connected to a single programming interface. Although the programming interface needed to configure this type of array will be relatively simple, the actual programming of the array will take considerably longer than that of a fully parallel array.
As will be appreciated, each different type of array will have specific advantages and disadvantages. Accordingly, a specific array may be particularly well suited for one type of application, but not for another.
For example, some tasks can be split into multiple sub-tasks, with each sub-task being able to be carried out concurrently (without being linked to the progress of other sub-tasks). Accordingly, for any task, there are a number of sub-tasks which must be carried out one after the other (in serial) and others which can be carried out concurrently (in parallel).
Exploiting the possibility of parallelism typically leads to the whole task being faster than if all sub-tasks were carried out serially. There is however usually some structural overhead associated with the parallelism. In the case of array configuration, this overhead takes the form of a more complex programming interface. It is a common engineering dilemma to have to strike a balance between the benefits and costs of parallelizing a task.
However, a problem arises when a device is designed for a plurality of applications or, for a customer who has, as of yet, not designed the application for which the device is being purchased. In such a scenario, an estimate of the optimal degree of parallelism must be made in order to produce a device. Any variation between the estimate and the actual need will cause either degraded system performance (i.e. the configuration time will be too long) or reduced cost-effectiveness (i.e. a larger circuit than necessary will have been produced).
Accordingly, there is a clear need for a device comprising an array of logic blocks which can be re-configured either in series, in parallel or in any combination thereof.